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| CXA2016S Sync Identification for CRT Display Description The CXA2016S is used for sync signal identification and waveform shaping in the CRT computers display for multi-scan system. There are three types of sync input signals for identification: separate sync, composite sync, and sync on video signals. Features * Power save function available (5 V power supply) * Clamp pulse output position selectable among sync interval, back porch interval, and AUTO. * Polarity information of sync signals is output. * Polarity and amplitude of input signals: Polarity Amplitude (Vp-p) V. separate sync: Positive/Negative 1 to 5 H. separate sync: Positive/Negative 1 to 5 Composite sync: Positive/Negative 1 to 5 Sync on video: Sync signals part of Negative 0.2 to 0.4 Video part 0 to 1.4 Applications CRT display monitor Pin Configuration (Top View) 1 2 3 VCC 22 VD 21 VSS IN 20 VSS OUT 19 PH 16 Polarity Check Exist Check 18 HD Logic VS IN PV 22 pin SDIP (Plastic) Absolute Maximum Ratings (Ta=25C) * Supply voltage VCC 12 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 962 mW Operating Conditions Supply voltage VCC 5 0.25 V Block Diagram PVC EVC VS IN PVC EVC 2 3 1 17 Polarity Check V. Ramp Generator Exist Check 21 VD 8 HD SEL 4 CS IN 5 6 7 8 PHC EHC Video IN HD SEL HD 18 CS IN 4 5 6 7 PV 17 PHC 9 ISC Clamp Pulse Generator Sync Sep Sync Check Bias 13 CLP OUT 14 CLP OUT PH 16 EHC CLP SEL 15 Video IN 15 CLP SEL 9 ISC 10 ISJ 11 GND CLP OUT 14 CLP OUT 13 VSS REF 12 Level Control 10 ISJ 19 VSS OUT 20 12 11 GND 22 VCC VSS IN VSS REF Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. --1-- E95422B78-TE CXA2016S Pin Description Pin No Symbol Pin voltage Equivalent circuit VCC 1k (Ta=25 C, VCC=5 V) Description 1 VS IN 2.6 V 1 100 V. separate sync (positive/negative polarity) as capacitor input. Amplitude is 1 to 5 Vp-p. GND VCC 1k 96k 2 PVC -- 2 1k 8k GND VCC 200 200 This pin connects a 0.22 F integrating capacitor for the vertical signal polarity check circuit to GND. When connecting the capacity at positive polarity, it is 2.9 V and at negative polarity, 120 mV. 3 EVC -- 3 200 1k V. ramp waveforms generation part of vertical signal exist check circuit. Generates ramp waveforms synchronously with the input signal cycle and connects 0.22 F to GND. GND VCC 1k 4 CS IN 2.6 V 4 100 Inputs composite sync (positive/negative polarity) and H. separate sync (positive/negative polarity) as capacitor input. Amplitude is 1 to 5 Vp-p. GND VCC 96k 5 PHC -- 5 1k 8k GND This pin connects a 0.1 F integrating capacitor for the horizontal signal polarity check circuit to GND. When connecting the capacity at positive polarity, it is 2.6 V and at negative polarity, 350 mV. A 33 k resistance and a nearly peak hold circuit for 0.22 F capacitor are connected to this pin for input signal exist check at CS IN input pin. When a signal is input at CS IN pin, a nearly peak hold is executed at 2.1 V to 2.7 V, a comparison is made with the 1.4 V reference voltage, and input signal exist is identified. VCC 1k 1k 6 EHC -- 100 1k 6 GND --2-- CXA2016S Pin No Symbol Pin voltage Equivalent circuit VCC 2k Description 7 Video IN -- 7 Inputs sync on video (sync at negative polarity). Connects in series a 1 F capacitor and a 270 resistance to input signals. GND VCC 8 HD SEL -- 8 1k GND VCC 2k 1k 9 ISC 1.2 V 9 100 50k GND VCC 4k 1k 10 ISJ 1.2 V 10 100 50k GND Selects output processing of HD (H. Drive Pulse) at a VD interval. Input at TTL level. When Low level is selected, HD is not output at a VD interval. When High level is selected, HD is output at the VD interval. Resistance connecting pin for reference current source of clamp pulse output circuit, and connects 12 k resistance to GND. When a 12 k resistance is connected, a 100 A current flows through this pin (pulse width is approximately 300 ns). Clamp pulse output pulse width is varied by changing the value of the resistance. Use a metal film resistor with an accuracy of 1 % Resistance connecting pin for reference current source and connecting 12 k resistance to GND. When the resistance is connected, a 100 A current flows through this pin. Use a metal film resistor with an accuracy of 1 % GND pin. 11 GND 0V -- VCC 12k 12 VSS REF 3.125 V 12 1k 20k GND Reference pin for V. sync separator of composite sync and video sync. --3-- CXA2016S Pin No 13 Symbol Pin voltage -- Equivalent circuit VCC Description CLP OUT 500 13 40k Clamp pulse output; Open collectortype pin at positive polarity. Clamp pulse output; Open collectortype pin at negative polarity. GND 14 CLP OUT -- 7k VCC 30k 20k 15 CLP SEL -- 15 1k 43k GND Selects output position of a clamp pulse. Input at TTL level. When Low level is selected, a clamp pulse is output at a back porch interval. When High level is selected, clamp pulse is output at a sync interval. See the Description of Operation for Input/Output Matrix. VCC 20k 16 17 PH PV -- 16 20k GND VCC 333 6k Output polarity information of horizontal and vertical sync signals. See the Description of Operation for Input/Output Matrix. 18 HD -- 18 6k HD (H. Drive Pulse) output; Push-pull type pin at positive polarity. 6k GND VCC 200 5k 19 VSS OUT -- 19 2.5k Composite sync or sync signal separated from video sync is output. Output is at positive polarity. GND VCC 17.5k 20 VSS IN -- 20 1k GND Input for V. sync separator comparator. Integrates the output at Pin 19 and inputs it. --4-- CXA2016S Pin No Symbol Pin voltage Equivalent circuit VCC 10k Description 21 VD -- 21 10k VD (V. Drive Pulse) output pin. Output is at positive polarity. 10k GND 22 VCC 5V -- Power supply pin. --5-- CXA2016S Electrical Characteristics No. Item Symbol (Ta=25 C, VCC=5 V. See the Electrical Characteristics Measurement Circuit.) Measurement contents Measure VD output peak value during V. separate sync input. Input signal A. (tw=60 s) Measure HD output peak value during sync on video input. Input signal C. (tw=1 s) Measurement point VD (Pin 21) Min. Typ. High level 4.9 Low level 0.1 High level 4.2 Low level 0.3 High level 4.9 Low level 0.3 High level 4.9 Low level 0.4 305 310 Max. Unit 1 VD output voltage EVD 4.3 -- -- 0.4 -- 0.5 -- 0.8 -- 0.9 380 380 V 2 HD output voltage EHD HD (Pin 18) CLAMP (Pin 13) 3.3 -- 4.3 -- V 3 Clamp pulse output voltage ECP Measure clamp pulse output peak value during composite sync input. Input signal B. (tw=1 s) V CLAMP (Pin 14) 4.3 -- V 4 Clamp pulse output pulse width tC Measure clamp pulse output pulse width during composite sync input. Input signal B. (tw=1 s) Measure delay difference between CS and HD during composite sync input. Or the time from CS (positive polarity) rise time (50 %) to HD output rise time (50 %). Input signal D. Measure delay difference between HD and clamp pulse during composite sync input. Or the time from HD output fall time (50 %) to clamp pulse output rise time1 (50 %). Input signal B. Sync signal polarity information is output. Measure high level voltage. (No load) Sync signal polarity information is output. Measure low level voltage. (No load) VCC=5 V. Measure current consumption during no signal input. CLAMP (Pin 13) CLAMP (Pin 14) 260 260 ns ns 5 HD delay thd HD (Pin 18) -- 75 100 ns 6 Clamp pulse delay CLAMP (Pin 13) CLAMP (Pin 14) PH, PV (Pins 16 and 17) PH, PV (Pins 16 and 17) VCC (Pin 22) -- 5.0 30 ns tcd1 -- 5.0 30 PN 7 Polarity identification output voltage PP 4.3 -- -- V -- -- 0.4 V 8 Current consumption ICC -- 26.5 45 mA 1 CLAMP is for the fall time. --6-- CXA2016S Types of Signal Source Signal Item V. SYNC IN (Pin 1) Composite SYNC IN (Pin 4) Video IN (Pin 7) A 1 1WV fv=40 Hz tWV=60 s Negative logic 1 Vp-p V fv=40 Hz tWV=60 s 1WV B 3, 4, 6 H 1WH Negative logic 1 Vp-p fH=50 kHz tWH=1 s Negative logic 1 Vp-p V 0.7V 0.2V 10H 60s 3H C 2 H fV=40 Hz tWV=60 s 15s 0.7V 0.2V 3s 1s fH=50 kHz tWH=1 s D 5 fH=50 kHz tWH=1 s Positive logic 1 Vp-p --7-- CXA2016S Electrical Characteristics Measurement Circuit HS Video or Sync CS VS 1 75 2.2 VS IN VCC 22 0.01 1 10 5V 2 PVC 0.22 VD 21 1k VD 3 EVC 0.22 VSS IN 20 4 75 1 CS IN VSS OUT 19 2.2k 3300p HD 5 0.1 75 33k 0.22 1 220 10k PHC HD 18 6 7 8 12k EHC PV 17 PV Video IN PH 16 PH HD SEL CLP SEL 15 0.1 9 12k ISC CLP OUT 14 1k CLAMP 10 ISJ CLP OUT 13 1k CLAMP 11 GND VSS Ref 12 0.01 --8-- CXA2016S Description of Operation Input signal * VS IN (Pin 1) fV : 40 to 200 Hz VS : 1 to 5Vp-p (positive/negative polarity) * HS IN (Pin 4) fH : 15k to 130 kHz VS : 1 to 5 Vp-p (positive/negative polarity) * CS IN (Pin 4) fH : 15 k to 130 kHz fV : 40 to 200 Hz VS : 1 to 5 Vp-p (positive/negative polarity) * Video IN (Pin 7) fH : 15 k to 130 kHz fV : 40 to 200 Hz VV : 0 to 1.4 Vp-p VS : 0.2 to 0.4 Vp-p Clamp Pulse Output * Clamp pulse (Pins 13 and 14) is output under the following conditions. Pin 13 is for open collector output and is at positive polarity. Pin 14 is for open collector output and is at negative polarity. td: Clamp pulse delays for 10 to 20 ns from HD. tw: Clamp pulse width varies depending on the value of the resistance connected to Pin 9. [O] indicates that input SYNC exists. [--] indicates no signal (no SYNC). [ ] has no relation with input signal. --9-- CXA2016S HD Select Function When HD SEL is Low, HD at the VD interval is not output. When HD SEL is High, HD at the VD interval is output. During separate sync output, HD is output regardless of HD SEL. Mode Matrix of SYNC Polarity Identification Signal VS IN (Pin 1) VS (positive polarity) CS IN (Pin 4) No signal HS (positive polarity) HS (negative polarity) No signal HS (positive polarity) HS (negative polarity) No signal COMP (positive polarity) COMP (negative polarity) PV out (Pin 17) Low Low Low High High High Low Low Low PH out (Pin 16) Low Low High Low Low High Low Low High VS (negative polarity) No signal Low level: 0 to 0.4 V, High level: VCC Input/Output Matrix VS IN O -- -- -- O O CS IN O O -- -- -- -- Video IN O -- O -- VD OUT VS CS Video (Video) VS VS HD OUT CS CS Video (Video) Video (Video) Note) The corresponding sync signals are input to VSIN and Video IN. [O] indicates that input SYNC exists. [--] indicates no signal. [ ] has no relation with input signal. --10-- CXA2016S Application Circuit CS Video or (G) HS VS 1 VS IN 2.2 75 VCC 22 VCC 5V VD OUT 2 PVC 0.22 VD 21 3 EVC 0.22 VSS IN 20 2.2k 4 CS IN 75 1 VSS OUT 19 3300p 5 PHC 0.1 33k 0.22 75 1 270 HD 18 HD OUT 6 EHC 7 Video IN 8 HD SEL 12k PV 17 PV PH 16 PH CLP SEL 15 0.1 CLP OUT 1k 9 ISC 12k 10 ISJ CLP OUT 14 CLP OUT 13 1k CLP OUT 11 GND VSS Ref 12 0.01 Use metal film resistor with an accuracy of 1% for the resistor marked . Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. --11-- CXA2016S Package Outline Unit : mm 22PIN SDIP (PLASTIC) + 0.1 0.05 0.25 - + 0.4 19.2 - 0.1 22 12 + 0.3 6.4 - 0.1 1 1.778 11 0.5 0.1 + 0.15 0.9 - 0.1 + 0.15 3.25 - 0.2 0.51 MIN + 0.4 3.9 - 0.1 7.62 0 to 15 Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-22P-01 SDIP022-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.95g --12-- |
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